Network on-Chip Architectures and Design Methodologies

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The huge number of transistors available on a single chip allows designers to integrate tens or hundreds of IP blocks together with large amounts of embedded memory. Following this trend, many semiconductor firms are proposing systems, based on few advanced cores, tightly interconnected and integrated on a single chip. This richness of the computational resources places tremendous demands on the communication resources as well.

The scalability and success of switch-based networks and packet-based communication in parallel computing has inspired the researchers to propose the Network-on-Chip (NoC) architecture as a viable solution to the complex on-chip communication problems. Although sharing some similarity (e.g. topology, packetized routing) with traditional direct network in multicomputers (sometimes called macro-networks), the NoC communication paradigm has specific properties which differentiate it from macro-networks.

Design-time specialization is an important factor for NoC paradigm, In fact most NoCs are developed specifically for one application or as a platform for a small class of applications. Consequently, the designer has a good understanding of the traffic characteristics and can use this information to customize the NoC accordingly. The existing techniques for macro-network optimization can not be directly applied to the NoC context. Thus, there is a need for NoC-specific design methodologies, that are critical in order to fully exploit the advantages the NoC paradigm can offer.

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